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| W55206B SERIAL VOICE SRAM (128K x 1 BIT) GENERAL DESCRIPTION The W55206B is a normal speed, low power CMOS static RAM organized as 128K x 1 bit that operates on a single 5V power supply. Manufactured using Winbond's high performance CMOS technology, the W55206B is designed for extensive use in voice recording applications. FEATURES * * Single 3.6V to 5.5V power supply Low power consumption * Fully static operation * Low data retention voltage * Easy to cascade PIN CONFIGURATION NC 1 18 NC NC 2 17 16 NC NC NC 3 NC 4 15 NC NC 5 14 NC VDD 6 13 VSS CS 7 12 CLK W/R EOP 8 9 11 DATA 10 ADDR PIN DESCRIPTION NO. 6 7 PIN VDD CS I/O PWR I Positive power supply Chip-inhibit for CS = 1; chip-select for CS = 0 or open (with internal pull-low resistor) DESCRIPTION -1- Publication Release Date: September 1996 Revision A1 W55206B Pin Description, continued NO. 8 9 10 11 12 13 PIN W/R EOP ADDR DATA CLK VSS I/O I O I I/O I PWR DESCRIPTION Write-in control for W/R = 1, read-out control for W/R = 0 End signal output Clock input for start address Bidirectional data pin Clock input for address increment Ground BLOCK DIAGRAM EOP W/R CS Control Circuits SRAM 128K x 1 bit DATA ADDR CLK Address Controller FUNCTIONAL DESCRIPTION * TRUTH TABLE CS H L L W/R X H L MODE Not selected Write Read DATA PIN High Z Data in Data out VDD CURRENT ISB IOP IOP * * When the chip is unselected, the W/R signal will be transmitted to the EOP pin. Before a read or write operation, the address counter must be reset by sending an ADDR pulse and setting DATA = 0. -2- W55206B * * * After power on, the read operation is disabled. A read operation may be performed only after a write operation is completed. In write-in operation, the EOP signal will change from low to high and remain high when the final address of the chip is encountered. It will change to low again with the next ADDR pulse. In read-out operation, the EOP pin will generate one pulse signal when the final address of the SRAM chip is encountered. The timing of the loading start address for write-in/read-out operations is shown below: * Load start address for write-in/read-out operations: CS ADDR CLK DATA ... ... EOP * Write-in operation: CS W/R ADDR CLK ... ... 128K DATA EOP -3- Publication Release Date: September 1996 Revision A1 W55206B * Read-out operation: CS W/R ADDR CLK ... ... 128K TEP DATA EOP * No operation (standby) CS W/R EOP ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature SYMBOL VDD-VSS VIN VO TOPR TSTG RATING -0.3 to +5.5 VSS -0.2 to VDD +0.2 VSS to VDD 0 to +70 -55 to +150 UNIT V V V C C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. -4- W55206B DC CHARACTERISTICS TA = 25 C, VDD = 5.0V, VSS = 0.0V PARAMETER Operating Voltage Operating Current VDD for Data Retention Data Retention Current Standby Current Input Voltage (for ADDR, CLK, W/R and CS pins) Input Current (for CS) Output Current (for EOP) SYMBOL VDD IOP VDR IDDDR ISB VIH VIL IIH IOH IOL CONDITIONS Fc = 1 MHz CS VDD -0.2V VDD 3V, CS 2.8V VI = 5.0V VO = 4.0V VO = 0.8V MIN. 3.6 2.4 2.8 -0.5 4 -4 LIMIT TYP. 5.0 2 6 -8 MAX. 5.5 15 5.5 10 10 6.0 +0.8 5 - UNIT V mA V A A V A mA AC CHARACTERISTICS Ta = 25 C, VDD = 5.0V, VSS = 0.0V PARAMETER Clock Frequency (for CLK and ADDR) Data Hold Time Data Hold Time Data Hold Time (for ADDR) Data Access Time Data Setup Time Data Setup Time (for ADDR) EOP Pulse Width (for ADDR) High Level Duration of Clock for CLK and ADDR Low Level Duration of Clock for CLK and ADDR W/R Signal Setup Time for Write Mode W/R Signal Setup Time for Write Mode Time Width Between ADDR and CLK Clock SYMBOL FC TWH TRH TAH TRA TWS TAS TEP TH TL TSUR TSUW TD CONDITIONS Write mode Read mode Read mode Write mode Read mode - MIN. 0 0 0 250 250 100 400 600 300 300 1 TYP - MAX. 1 80 - UNIT MHz nS nS nS nS nS nS nS nS nS nS nS S TYPICAL APPLICATION CIRCUIT (For reference only) Publication Release Date: September 1996 Revision A1 -5- W55206B W51205901A/ W51205903A DATA CLK ADDR W/R CS EOP W55206B DATA CLK ADDR W/R CS EOP * W51205901A/W51205903A substrate connected to VSS for C.O.B. * W55206B substrate connected to VDD for C.O.B. Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792697 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006 Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. -6- |
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